# Computer System Architecture Set 17

### Questions 161 to 170

161.
Using Karnaugh map SOP form of the expression
(B + C + D) (B’ + C + D’) (A’ + B + C’ + D’) (A + B’ + E’) (A + B’ + D’) will be
 (a) BCD + B’CD + A’BC’D’ + AB’E’ + AB’D’ (b) B’C’D’ + BC’D + AB’CD + A’BE’ + A’BD (c) B’C’D + A’B’C + ABC + BD’E’ + ACD’ + ABD’ (d) B’C’D’ + BCD + AB’CD + A’BE + A’BD (e) BCD + B’C’D + A’BCD’ + ABE + AB’D’.
162.
The number of input variables which a NOT gate can have is
 (a) One (b) Two (c) Three (d) Four (e) Any number.
163.
The unique output for a NAND logic gate is a 0
 (a) When all inputs are 0 (b) When all the inputs are 1 (c) When any one input is 0 (d) When any one input is 1 (e) All of the above.
164.
The states of a bus may be
 (a) Logic 0, logic 1 and Low impedence (b) Logic 0, logic –1 and high impedence (c) Logic –2, logic –1 and high impedence (d) Logic –1, logic 1 and high impedence (e) Logic 0, logic 1 and high impedence.
165.
The binary pattern 101110 is an answer received after adding two numbers in a 6-bit two’s complement system. The answer in decimal system is
 (a) – 45 (b) – 44 (c) – 18 (d) – 13 (e) + 45.
166.
A 4-bit ALU which is based on 1’complement arithmetic is used to do the following addition.
1101
+1011
 (a) Range overflow (b) 16 (c) –16 (d) 8 (e) 24.
167.
Using Boolean algebra the reduced expression for function AB’C + ABC can be realized by using how many number of gates?
 (a) 7 (b) 3 (c) 2 (d) 11 (e) 8
168.
RISC stands for
 (a) Reduced Instruction Sign Computers (b) Reduced Instruction Set Computers (c) Reduced Instruction Set Carry (d) Reduced Invalid Set Computers (e) Reset Instruction Set Computers.
169.
A binary system based on Two’s complement arithmetic gives the answer 110010. The decimal equivalent(s) of this answer is
 (a) 13 (b) –13 (c) –16 (d) –18 (e) –14.
170.
Which of the following statement is false?
 (a) Combinational circuits has memory (b) Sequential circuits has memory (c) Sequential circuits is a function of time (d) Combinational circuits does not require feed back paths (e) Sequential circuits require feed back paths.

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