Computer System Architecture Set 21

Questions 201 to 210



201.
When a large number of registers is included in the CPU, it is most efficient to connect them through a ______.
(a)    ALU                       (b)  Memory Register  (c)  STACK
(d)    QUEUE                 (e)  Bus system.
202.
The register that keeps track of the address of next instruction to be executed is ______ .
(a)    AC                          (b)  PC                            (c)  IR                             (d)  AR                           (e)  DR.
203.
The correspondence between the main memory blocks and those in the cache is specified by  _________.
(a)    Miss penalty                                                 (b)  Replacement algorithms                              (c)  Hit rate
(d)    Page fault                                                      (e)  Mapping functions.
204.
Which one of the following can be called as a peripheral?
(a)    Control unit                                                  (b)  Arithmetic unit      (c)  Speaker                  
(d)  Logic unit                                                        (e)  Main memory.
205.
The set of physical addresses is called
(a)    Disk Space                                   (b)  Address Space                                                               (c)  Pages
(d)    Frames                                         (e)  Location.
206.
The device that is allowed to initiate data transfer on the bus is called ___________.
(a)    Bus master                  (b)  Bus arbitration              (c)  Bus cycle
(d)    Bus request                  (e)  Parallel bus.
207.
The DMA transfer technique where transfer of one word data at a time is called ______.
(a)    Cycle stealing                                              (b)  Memory stealing                                           (c)  Hand-shaking
(d)    Inter-leaving                                                (e)  Bus stealing.
208.
______ interface is used to connect the processor to I/O devices that require transmission of data one bit at a time.
(a)    Parallel                         (b)  Serial                                               (c)  Output                             (d)  Input                                  (e)  Bus.
209.
In based addressing mode, instruction contains ________.
(a)    Base address                                               (b)  Displacement                                    (c)  Absolute address
(d)    Relative address                                         (e)  Indirect address.
210.
A hand-shake based protocol for data transfer is an example of ______ type of data transfer.
(a)    Synchronous               (b)  Asynchronous                                               (c)  Serial
(d)    Parallel                         (e)  Indirect.


Answers



201.
Answer :   (a)
Reason :            All registers in a CPU are connected through ALU..
202.
Answer :   (b)
Reason :            Program Counter contains the address of the next instruction to be executed..
203.
Answer :   (e)
Reason :            The corresponding  between the main memory blocks and those in the cache is specified by a mapping function, because the basic characteristic of cache memory is fast access time. Therefore, very little or no time must be wasted when searching for words in the cache.
204.
Answer :   (c)
Reason :   Speakers can be called as a peripheral as all others are part of the system.
205.
Answer :   (b)
Reason :            The collection of address spaces in a physical memory is called address space.
206.
Answer :   (a)
Reason :            The Bus master is allowed to initiate data transfer on the bus.
207.
Answer :   (a)
Reason :            Transfer of one word data at a time using DMA transfer technique is called Cycle Stealing.
208.
Answer :   (b)
Reason :            Serial interface transfers one bit at a time, whereas others can handle more than one bit.
209.
Answer :   (b)
Reason :            In a  based addressing mode the displacement is the address field.
210.
Answer :   (b)
Reason :            Asynchronous data transfer

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