Computer System Architecture Set 9

Questions 81 to 90


81.
A machine cycle refers to
(a)
Fetching an instruction
(b)
Clock speed
(c)
Fetching, decoding and executing  an instruction
(d)
Executing and instruction
(e)
Decoding an instruction.
82.
The System bus is made up of
(a)
Control bus
(b)
Address bus
(c)
Both Control bus and Address bus
(d)
Control bus, Data bus and Address bus
(e)
Data bus.
83.
The code used to boot up a computer is stored in
(a)
RAM
(b)
ROM
(c)
PROM
(d)
EPROM
(e)
EEPROM.
84.
In accessing a disk block the longest delay is due to
(a)
Rotation time
(b)
Seek time
(c)
Transfer time
(d)
Clock speed
(e)
Access time.
85.
Which of the following is/are not part(s) of the CPU?
(a)
ALU
(b)
The Control unit
(c)
The Registers
(d)
System bus
(e)
All of the above.
86.
Memory mapped  I/O  involves transferring of
(a)
Information between memory locations
(b)
Information between registers and memory
(c)
Information between CPU and I/O devices
(d)
Information between CPU and  Memory
(e)
Information between I/O devices and CPU.
87.
Name the type of memory that can be erased with the electric discharge?
(a)
ROM
(b)
EPROM
(c)
RAM
(d)
EEPROM
(e)
PROM.
8.
What is the units for measuring the CPU performance?
(a)
BPS
(b)
MIPS
(c)
MHz
(d)
VLSI
(e)
KHz.
89.
The read/write line belongs to
(a)
The data bus
(b)
The control bus
(c)
The address bus
(d)
CPU bus
(e)
System bus.
90.
Busy waiting is a technique
(a)
To allow the CPU wait for a busy device
(b)
To allow a busy device wait for the CPU
(c)
To keep an idle device busy
(d)
To improve CPU performance
(e)
To keep a device busy.

Answers


81.
Answer :   (c)
Reason  :  A machine cycle refers to Fetching, decoding and executing  an instruction.
82.
Answer :   (d)
Reason  :  System bus consists of a Control bus, Data bus and a Address bus.
83.
Answer :   (b)
Reason  :  The bootable code is stored in ROM.
84.
Answer :   (e)
Reason  :  Access time.
85.
Answer :   (d)
Reason  :  System bus is not a part of a cpu .
86.
Answer :   (e)
Reason  :  Memory mapped I/O involves transferring information between I/O devices and CPU .
87.
Answer :   (d)
Reason  :  EEPROM is the type of memory whose contents is erased with the passage of electiricity.
88.
Answer :   (c)
Reason  :  CPU performance is measured in MHz
89.
Answer :   (c)
Reason  :  The read / write line belongs to the address bus.a
90.
Answer :   (a)
Reason  :  Busy waiting is to allow the CPU wait for a busy device.

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