Computer System Architecture Set 6

Questions 51 to 60


51.
To convert octal code to binary code which of the following digital functions should be used?
(a)
Decoder
(b)
Encoder
(c)
Multiplexer
(d)
Demultiplexer
(e)
Half adder.
52.
A full-adder is simply a connection of two half-adders joined by a,
(a)
AND gate
(b)
OR gate
(c)
NAND gate
(d)
NOR gate
(e)
XOR gate.
53.
The correspondence between the main memory blocks and those in the cache is specified by a
(a)
Miss penalty
(b)
Replacement algorithms
(c)
Hit rate
(d)
Page fault
(e)
Mapping functions.
54.
The number of 256*4 RAM chips required to construct 2KB CACHE is
(a)
  8
(b)
  2
(c)
  4
(d)
16
(e)
32.
55.
The set of physical addresses is called
(a)
Disk Space
(b)
Address Space
(c)
Pages
(d)
Frames
(e)
Location.
56.
What is the name of device that is allowed to initiate data transfer on the bus?
(a)
Bus Master
(b)
Bus Arbitration
(c)
Bus Cycle
(d)
Bus Request
(e)
Parallel Bus.
57.
The DMA transfer technique where transfer of one word data at a time is called
(a)
Cycle stealing
(b)
Memory stealing
(c)
Hand-shaking
(d)
Inter-leaving
(e)
Bus stealing.
58.
What interface is used to connect the processor to I/O devices that require transmission of data one bit at a time?
(a)
Parallel
(b)
Serial
(c)
Output
(d)
Input
(e)
Bus.
59.
What are the building blocks of combinational circuits?
(a)
Flip-flops
(b)
Logic gates
(c)
Latches
(d)
Registers
(e)
Inputs.
60.
The transfer of new information into the register is called
(a)
Execution
(b)
Loading
(c)
Shifting
(d)
Configuring
(e)
Uploading.

Answers


51.
Answer :   (a)
Reason:    Decoder.
52.
Answer :   (b)
Reason:    A full-adder is simply a connection of two half-adders joined by a OR gate, and other half-adder simplify the AND gate also.
53.
Answer :   (e)
Reason:    The corresponding  between the main memory blocks and those in the cache is specified by a mapping function, because the basic characteristic of cache memory is fast access time. Therefore, very little or no time must be wasted when searching for words in the cache.
54.
Answer :   (d)
Reason:    16 RAM chips of size 256*4 are needed to construct a CACHE of size 2KB
55.
Answer :   (b)
Reason:    The collection of address spaces in a physical memory is called address space.
56.
Answer :   (a)
Reason:    The Bus master is allowed to initiate data transfer on the bus.
57.
Answer :   (a)
Reason:    Transfer of one word data at a time using DMA transfer technique is called Cycle Stealing.
58.
Answer :   (b)
Reason:    Serial interface transfers one bit at a time, whereas others can handle more than one bit.
59.
Answer :   (b)
Reason:    In a  based Logical gates are building blocks of combinational circuits whereas, flipflops are combination of logic gates, registers are memory storages.
60.
Answer :   (b)
Reason:    Entering new information into a register is called loading.

<< Prev  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26

27  28  29  30  31  32  33  34  35  36  37  38  39  Next >>


No comments :

What you think about these Questions and Answers ? Let me know in comments.

Post a Comment